Intrinsic ID Collaborates with Synopsys to Boost SoC Security and Accelerate Time to Market

Intrinsic ID, the world’s leading provider of Physical Unclonable Function (PUF) security IP today announced a renewed collaboration with Synopsys, Inc. to provide pre-verified PUF and hardware secure module (HSM) security solutions that protect connected devices against advanced security threats.

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SAN JOSE, Calif. and SUNNYVALE, Calif., – May 12, 2022 – QuickLogic Corporation (NASDAQ: QUIK), a developer of ultra-low power multi-core voice-enabled SoCs, embedded FPGA IP, and Endpoint AI solutions, today announced that it has partnered with Intrinsic ID, the world’s leading provider of Physical Unclonable Function (PUF) security IP, to provide security options for devices incorporating embedded FPGA (eFPGA) technology. These options range from secure key generation based on SRAM PUF to full security solutions including bitstream encryption, key wrapping, authentication tags, key verification, and data encryption/decryption for storage within the device or for board or system-level communications. This partnership has created a seamless integration of the solutions of both companies, allowing QuickLogic’s eFPGA customers to add security functionality without any further integration effort.

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I was just chatting with the folks at Synaptics about their recently launched FlexSense family of teeny-tiny multi-modal smart sensor processors. Actually, I was thinking about using “Teeny-Tiny Multi-Modal Smart Sensor Processors” as the title for this column, but I saw “Reimagining How Humans Engage with Machines and Data” on some of their materials and I ended up flipping a metaphorical coin. (I defy anyone to tell me that this opening paragraph won’t bring tears of joy to the bean counters who stride the corridors of the SEO domain, especially those interested in human-machine interfaces (HMIs), the Internet of Things (IoT), and artificial intelligence (AI) on the edge, Ha!)

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Intrinsic ID and Rambus Raise the Bar for Hardware Security with Integration of PUF Technology and Rambus Root of Trust

Easing integration efforts for two industry-leading security solutions enables broader coverage of both data and hardware for robust security in semiconductor chip designs
SUNNYVALE, Calif., November 16, 2021 – Intrinsic ID, the world’s leading provider of Physical Unclonable Function (PUF) security IP today announced the availability of integrated solutions that combine the Intrinsic ID PUF technology with Rambus Root of Trust security cores. Customers will now be able to seamlessly implement the Intrinsic ID QuiddiKey® hardware IP with Rambus Root of Trust Solutions to ensure broader coverage of both data and hardware security in their chip designs.

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Did the abundance of abbreviations with which the title of this column abounds cause you to pause for a moment and think, “Say, what?” Well, that’s just what I thought when the guys and gals at Synaptics introduced me to their AS33970 Tahiti System-on-Chip (SoC) device, but first…

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Security cameras and image sensors are pretty stupid, as we’ve explained before. Yet they’re important for a range of applications that have nothing to do with taking selfies at the beach.

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Astera Labs Aries Smart Retimers resolve signal integrity issues for high-performance server, storage, cloud and workload optimized systems
Avery PCIe and CXL Verification IP enabled Astera Labs to get to market faster
Tewksbury, MA., April 28, 2021 — Avery Design Systems, a leader in functional verification solutions, today announced that Astera Labs, a pioneer in connectivity solutions for intelligent systems, successfully used Avery’s Compute Express Link™ (CXLTM) 2.0 and PCI Express® (PCIe®) 5.0 Verification IP (VIP) and services in developing its Aries Smart Retimer portfolio.

The Avery CXL 2.0 and PCIe 5.0 VIP is a comprehensive solution supporting SoC verification comprised of SystemVerilog-based/UVM agents and compliance testsuites as well CXL system simulation running the latest CXL-enabled Linux kernel on QEMU-to-RTL co-simulation environment.

“The launch of our Aries CXL 2.0 Smart Retimer portfolio is a game changer for mainstreaming specialized workloads in complex heterogeneous compute and composable disaggregation system topologies,” said Kalyan Mulam, VP of Engineering, Astera Labs. “Working with a leading verification IP provider like Avery helped us streamline the design and verification process to deliver our Aries CXL 2.0 Smart Retimers to market and enable the rapidly emerging CXL ecosystem.”

“We are excited to collaborate with Astera Labs on PCIe and CXL verification of their purpose-built retimers, which play a crucial role in rapidly expanding the CXL datacenter ecosystem in 2021 and beyond,” said Chris Browy, vice president of sales and marketing at Avery Design Systems.

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My distinguished guest in this week’s Fish Fry podcast is Intrinsic-ID CEO Pim Tulys. Pim and I discuss the role of hardware-based security in today’s EE ecosystem, where physical unclonable functions are headed in the future, and what Intrinsic ID’s PUF Cafe is all about. Also this week, we take a closer look at the details of a new experiment that might finally bridge the gap between robotics and quantum mechanics. (Spoiler Alert: robots can learn faster with the help of quantum mechanics!)

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